The use of digital filters is widespread for a number of reasons, not least of which is that a digital filter can perform filtering functions that may not be practically realizable with analog filters. Digital filters may be employed in signal processing circuitry as well as other circuits where the filtering effect can be expressed as a mathematical function or algorithm. In a typical application, the digital filter modifies an intermediate form of a signal by performing a mathematical operation (e.g., multiplication, addition, etc.) in which a coefficient is combined mathematically with the intermediate signal, or a portion thereof. Usually, there is more than one coefficient being mathematically combined with more than one portion of the signal and hence a set of these coefficients is used to form a digital filter. The term “coefficient word” typically refers to a number having a specific number of binary digits (bits). Digital filters are typically designed with certain design criteria in mind, such as the operating frequency of the filter, a known quality factor (“Q”) of the filter, and a known sampling frequency. Using these criteria, a set of coefficient words can be determined to achieve the necessary filtering of a signal.
However, as digital filters are implemented in applications that require increasingly larger coefficient words, more hardware resources, and therefore higher cost, are required to realize the digital filter. For example, the audio frequency range is nominally taken to span the range from 20 Hz to 20 KHz. Typical digital audio sample rates may be 44.1 KHz, 48 KHz or higher. Using a sample rate of 48 KHz as a nonlimiting example, the ratio of the Nyquist limit frequency (24 KHz) to the minimum frequency in the audio frequency range (20 Hz) is 1200 to 1. When designing a digital filter with such a wide frequency ratio, large coefficient word sizes are necessary in order to prevent undesired gain error in the filter response, typically at the lowest of frequencies.
The variety of applications for digital filters continues to grow as the speed, size, complexity, and usefulness of digital filters are improved. Some of these applications include audio filters, video filters, cell phones, radios, transmitters, receivers, motor controllers, audio compact disc players, etc. Digital filters with large coefficient word sizes may require more complex and expensive field programmable gate arrays (“FPGAs”), more costly microprocessors that can operated with large coefficient word sizes, or may require designing circuitry with double the number of components in order to accommodate large coefficient word sizes. In these and other applications, it is highly desirable to minimize the use of hardware resources and so rein in the cost of the digital filter and therefore the overall cost of the device.
Typically, the coefficients used for a digital filter are signed binary numbers in a “two's complement” format, as is known in the art. These coefficients include one bit, sometimes designated the “sign bit”, which carries information relating to the sign value of the coefficient and the remaining bits, sometimes designated the “magnitude bits”, which carry information relating to the magnitude of the coefficient. In certain applications, multiple coefficients must be combined (e.g., via a multiplier/divider circuit and/or an adder/subtracter circuit) and the known prior art systems perform these combining functions on the entire coefficient word, i.e., on the sign bit and the magnitude bits. Thus, the size of a multiplier input, for example, must be wide enough to accommodate all the magnitude bits and the sign bit of a given coefficient word. As a non-limiting example, if a coefficient word size is 19 bits, i.e., 1 sign bit and 18 magnitude bits, and the width of a multiplier input is only 18 bits wide, then a second multiplier will need to be incorporated into the circuitry in order to accommodate the 19 bit wide coefficient word. This results in inefficiencies and unnecessary expense.
Accordingly, it is an object of the present disclosure to implement a method and apparatus wherein the use of a larger coefficient word size can be realized so as to avoid having to incur the inefficiencies and cost associated with using additional hardware resources while maintaining an acceptable gain error in the filter response.
It is also an object of the present disclosure to provide a method and/or system for combining multiple coefficient words using only the magnitude bits of each of the coefficient words and using the sign bits of each of the coefficient words to modify the output of the combined magnitude bits. Additionally, the magnitude bits of a first coefficient word may be combined (e.g., multiplied) with a first intermediate term word (either signed or unsigned) to form a first resultant word. Similarly, the magnitude bits of a second coefficient word may be combined (e.g., multiplied) with a second intermediate term word (either signed or unsigned) to form a second resultant word. The first and second resultant words may then be combined to form a third resultant word where the sign bits from the first and second coefficient words may be combined to modify the third resultant word.
It is another object of the present disclosure to provide a method for combining binary numbers including receiving a first binary number having a first sign bit and a predetermined number N1 of magnitude bits, receiving a second binary number having a second sign bit and a predetermined number N2 of magnitude bits, combining the N1 magnitude bits with a third binary number having predetermined number M1 bits to thereby form a fourth binary number, combining the N2 magnitude bits with a fifth binary number having predetermined number M2 bits to thereby form a sixth binary number, decoding the first and second sign bits to thereby form a control signal, combining the fourth binary number with the sixth binary number as a function of the control signal to thereby form a seventh binary number, selectively applying a two's complement negation to the seventh binary number as a function of the first sign bit to thereby provide an eighth binary number, and providing the eighth binary number to a digital processing device to thereby modify the output of said digital processing device.
It is yet another object of the present disclosure to provide a method for combining binary numbers including receiving a first binary number having a first sign bit and a predetermined number N1 of magnitude bits, receiving a second binary number having a second sign bit and a predetermined number N2 of magnitude bits, combining the N1 magnitude bits with a third binary number having predetermined number M1 bits to thereby form a fourth binary number, combining the N2 magnitude bits with a fifth binary number having predetermined number M2 bits to thereby form a sixth binary number, decoding the first and second sign bits to thereby form a first control signal, combining the fourth binary number with the sixth binary number as a function of the first control signal to thereby form a seventh binary number, decoding the first sign bit and a third sign bit to thereby form a second control signal, combining the seventh binary number with an eighth binary number as a function of the second control signal to thereby form a ninth binary number, selectively applying a two's complement negation to the ninth binary number as a function of the first sign bit to thereby provide a tenth binary number, and providing the tenth binary number to a digital processing device to thereby modify the output of the digital processing device.
It is still another object of the present disclosure to provide a system for combining binary numbers where the system includes a first coefficient register capable of storing a first binary number having a first sign bit and a predetermined number N1 of magnitude bits, a second coefficient register capable of storing a second binary number having a second sign bit and a predetermined number N2 of magnitude bits, a first combiner operatively connected to the first coefficient register wherein the first combiner combines the N1 magnitude bits with a third binary number having predetermined number M1 bits and provides a fourth binary number as an output, a second combiner operatively connected to the second coefficient register wherein the second combiner combines the N2 magnitude bits with a fifth binary number having predetermined number M2 bits and provides a sixth binary number as an output, a decoder operatively connected to the first and second coefficient registers wherein the decoder decodes the first and second sign bits and provides a control bit as an output, a third combiner operatively connected to the first and second combiners and the decoder wherein the third combiner combines the fourth and sixth binary numbers as a function of the control bit and provides a seventh binary number as an output, and a two's complement negation control element operatively connected to the third combiner and the first coefficient register wherein the two's complement negation control element selectively applies a two's complement negation to the seventh binary number as a function of the first sign bit.
It is a further object of the present disclosure to provide a system for combining binary numbers where the system includes a first coefficient register capable of storing a first binary number having a first sign bit and a predetermined number N1 of magnitude bits, a second coefficient register capable of storing a second binary number having a second sign bit and a predetermined number N2 of magnitude bits, a first combiner operatively connected to the first coefficient register wherein the first combiner combines the N1 magnitude bits with a third binary number having predetermined number M1 bits and provides a fourth binary number as an output, a second combiner operatively connected to the second coefficient register wherein the second combiner combines the N2 magnitude bits with a fifth binary number having predetermined number M2 bits and provides a sixth binary number as an output, a decoder operatively connected to the first and second coefficient registers wherein the decoder decodes the first and second sign bits and provides a control bit as an output, a third combiner operatively connected to the first and second combiners and the decoder wherein the third combiner combines the fourth and sixth binary numbers as a function of the control bit and provides a seventh binary number as an output, a second decoder operatively connected to the first coefficient register and having an input terminal adapted to receive a third sign bit wherein the second decoder decodes the first and third sign bits and provides a second control bit as an output, a fourth combiner operatively connected to the third combiner and the second decoder and having an input terminal adapted to receive an eighth binary number wherein the fourth combiner combines the seventh and eighth binary numbers as a function of the second control bit and provides a ninth binary number as an output, and a second two's complement negation control element operatively connected to the fourth combiner and the first coefficient register wherein the second two's complement negation control element selectively applies a two's complement negation to the ninth binary number as a function of the first sign bit.
These and many other advantages of the present disclosure will be readily apparent to one skilled in the art to which the disclosure pertains from a perusal of the claims, the appended drawings, and the following detailed description.